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general description the max1221/MAX1223/max1343 integrate a multichan- nel, 12-bit, analog-to-digital converter (adc) and a 12-bit, digital-to-analog converter (dac) in a single ic. the devices also include a temperature sensor and config- urable general-purpose i/o ports (gpios) with a 25mhz spi-/qspi-/microwire-compatible serial inter- face. the adc is available in a 12 or an eight input-chan- nel version. the dac outputs settle within 2.0?, and the adc has a 225ksps conversion rate. all devices include an internal reference (2.5v) providing a well-regulated, low-noise reference for both the adc and dac. programmable reference modes for the adc and dac allow the use of an internal reference, an exter- nal reference, or a combination of both. features such as an internal ?? accurate temperature sensor, fifo, scan modes, programmable internal or external clock modes, data averaging, and autoshutdown allow users to minimize both power consumption and processor requirements. the low glitch energy (4nv s) and low digi- tal feedthrough (0.5nv s) of the integrated dacs make these devices ideal for digital control of fast-response closed-loop systems. the devices are guaranteed to operate with a supply volt- age from +2.7v to +5.25v. the devices consume 2.5ma at 225ksps throughput, only 22? at 1ksps throughput, and under 0.2? in the shutdown mode. the max1221/ max1343 offer four gpios that can be configured as inputs or outputs. the max1221/MAX1223/max1343 are available in 36-pin thin qfn packages. all devices are specified over the -40? to +85? temperature range. applications closed-loop controls for optical components and base stations system supervision and control data-acquisition systems features ? 12-bit, 225ksps adc analog multiplexer with true-differential track/hold (t/h) 12 single-ended channels or six differential channels (unipolar or bipolar) (MAX1223) eight single-ended channels or four differential channels (unipolar or bipolar) (max1221/max1343) excellent accuracy: ?.5 lsb inl, ?.5 lsb dnl ? 12-bit, octal, 2? settling dac (max1221/MAX1223) ultra-low glitch energy (4nv s) power-up options from zero scale or full scale excellent accuracy: ?.5 lsb inl ? internal reference or external single-ended/ differential reference internal reference voltage 2.5v ? internal ?? accurate temperature sensor ? on-chip fifo capable of storing 16 adc conversion results and one temperature result ? on-chip channel-scan mode and internal data-averaging features ? analog single-supply operation +2.7v to +5.25v ? 2.7v to av dd digital supply ? 25mhz, spi/qspi/microwire serial interface ? autoshutdown between conversions ? low-power adc 2.5ma at 225ksps 22? at 1ksps 0.2? at shutdown ? low-power dac: 1.5ma ? evaluation kit available (order max1258evkit) max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ________________________________________________________________ maxim integrated products 1 ordering information/selector guide 19-4010; rev 1; 12/07 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configurations appear at end of data sheet. part pin-package ref voltage (v) analog supply voltage (v) resolution bits** adc channels dac channels gpios pkg code max1221 betx 36 thin qfn-ep* 2.5 2.7 to 5.25 12 8 8 4 t3666-3 MAX1223 betx 36 thin qfn-ep* 2.5 2.7 to 5.25 12 12 8 0 t3666-3 max1343 betx 36 thin qfn-ep* 2.5 2.7 to 5.25 12 8 4 4 t3666-3 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. autoshutdown is a trademark of maxim integrated products, inc. note: all devices are specified over the -40? to +85? operating temperature range. * ep = exposed pad. ** number of resolution bits refers to both dac and adc.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dgnd to agnd.....................................................-0.3v to +0.3v dv dd to av dd .......................................................-3.0v to +0.3v digital inputs to dgnd.............................................-0.3v to +6v digital outputs to dgnd .........................-0.3v to (dv dd + 0.3v) analog inputs, analog outputs and ref_ to agnd...............................................-0.3v to (av dd + 0.3v) maximum current into any pin (except agnd, dgnd, av dd , dv dd , and out_) ...........................................................50ma maximum current into out_.............................................100ma continuous power dissipation (t a = +70?) 36-pin thin qfn (6mm x 6mm) (derate 26.3mw/? above +70?) ......................2105.3mw operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units adc dc accuracy (note 1) resolution 12 bits integral nonlinearity inl ?.5 ?.0 lsb differential nonlinearity dnl ?.5 ?.0 lsb offset error ?.5 ?.0 lsb gain error (note 2) ?.5 ?.0 lsb gain temperature coefficient ?.8 ppm/? channel-to-channel offset ?.1 lsb dynamic specifications (10khz sine-wave input, v in = 2.5v p-p , 225ksps, f clk = 3.6mhz) signal-to-noise plus distortion sinad 70 db total harmonic distortion (up to the fifth harmonic) thd -76 dbc spurious-free dynamic range sfdr 72 dbc intermodulation distortion imd f in1 = 9.9khz, f in2 = 10.2khz 76 dbc full-linear bandwidth sinad > 70db 100 khz full-power bandwidth -3db point 1 mhz conversion rate (note 3) external reference 0.8 ? power-up time t pu internal reference (note 4) 218 c onver si on cl ock cycl es note: if the package power dissipation is not exceeded, one output at a time may be shorted to av dd , dv dd , agnd, or dgnd indefinitely.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) parameter symbol conditions min typ max units acquisition time t acq (note 5) 0.6 ? internally clocked 5.5 conversion time t conv externally clocked 3.6 ? external-clock frequency f clk externally clocked conversion (note 5) 0.1 3.6 mhz duty cycle 40 60 % aperture delay 30 ns aperture jitter < 50 ps analog inputs unipolar 0 v ref input voltage range (note 6) bipolar -v ref / 2 v ref / 2 v input leakage current ?.01 ? ? input capacitance 24 pf internal temperature sensor t a = +25? ?.7 measurement error (notes 5, 7) t a = t min to t max ?.0 ?.0 ? temperature resolution 1/8 ?/lsb internal reference ref1 output voltage (note 8) 2.482 2.50 2.518 v ref1 voltage temperature coefficient tc ref ?0 ppm/? ref1 output impedance 6.5 k ref1 short-circuit current v ref = 2.5v 0.39 ma external reference ref1 input voltage range v ref1 ref mode 11 (note 4) 1 av dd + 0.05 v ref mode 01 1 av dd + 0.05 ref2 input voltage range (note 4) v ref2 ref mode 11 0 1 v
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) parameter symbol conditions min typ max units v ref = 2.5v, f sample = 225ksps 25 80 ref1 input current (note 9) i ref1 acquisition between conversions ?.01 ? ? v ref = 2.5v, f sample = 225ksps 25 80 ref2 input current i ref2 acquisition between conversions ?.01 ? ? dac dc accuracy (note 10) resolution 12 bits integral nonlinearity inl ?.5 ? lsb differential nonlinearity dnl guaranteed monotonic ?.0 lsb offset error v os (note 8) ? ?0 mv offset-error drift ?0 ppm of fs/? gain error ge (note 8) ? ?0 lsb gain temperature coefficient ? ppm of fs/? dac output no load 0.02 av dd - 0.02 output voltage range 10k load to either rail 0.1 av dd - 0.1 v dc output impedance 0.5 capacitive load (note 11) 1 nf resistive load to agnd r l av dd = 2.7v, v ref = 2.5v, gain error < 1% 2000
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) parameter symbol conditions min typ max units from power-down mode, av dd = 5v 25 wake-up time (note 12) from power-down mode, av dd = 2.7v 21 ? 1k output termination programmed in power-down mode 1 k 100k output termination at wake-up or programmed in power-down mode 100 k dynamic performance (notes 5, 13) output-voltage slew rate sr positive and negative 3 v/? output-voltage settling time t s to 1 lsb, 400 - c00 hex (note 7) 2 5 ? digital feedthrough code 0, all digital inputs from 0 to dv dd 0.5 nv s major code transition glitch impulse between codes 2047 and 2048 4 nv s from v ref 660 output noise (0.1hz to 50mhz) using internal reference 720 ? p-p from v ref 260 output noise (0.1hz to 500khz) using internal reference 320 ? p-p dac-to-dac transition crosstalk 0.5 nv s internal reference ref1 output voltage 2.482 2.50 2.518 v ref1 temperature coefficient tc ref ?0 ppm/? ref1 short-circuit current v ref = 2.5v 0.39 ma external-reference input ref1 input voltage range v ref1 ref modes 01, 10, and 11 (note 4) 0.7 av dd v ref1 input impedance r ref1 70 100 130 k digital interface digital inputs (sclk, din, cs , cnvst , ldac ) input-voltage high v ih dv dd = 2.7v to 5.25v 2.4 v dv dd = 3.6v to 5.25v 0.8 input-voltage low v il dv dd = 2.7v to 3.6v 0.6 v input leakage current i l ?.01 ?0 ? input capacitance c in 15 pf digital output (dout) (note 14) output-voltage low v ol i sink = 2ma 0.4 v
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 6 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) parameter symbol conditions min typ max units output-voltage high v oh i source = 2ma dv dd - 0.5 v tri-state leakage current ?0 ? tri-state output capacitance c out 15 pf digital output ( eoc ) (note 14) output-voltage low v ol i sink = 2ma 0.4 v output-voltage high v oh i source = 2ma dv dd - 0.5 v tri-state leakage current ?0 ? tri-state output capacitance c out 15 pf digital outputs (gpio_) (note 14) i sink = 2ma 0.4 gpioc_ output-voltage low i sink = 4ma 0.8 v gpioc_ output-voltage high i source = 2ma dv dd - 0.5 v gpioa_ output-voltage low i sink = 15ma 0.8 v gpioa_ output-voltage high i source = 15ma dv dd - 0.8 v tri-state leakage current ?0 ? tri-state output capacitance c out 15 pf power requirements (note 15) digital positive-supply voltage dv dd 2.7 av dd v idle, all blocks shut down 0.2 4 a digital positive-supply current di dd only adc on, external reference 1 ma analog positive-supply voltage av dd 2.70 5.25 v idle, all blocks shut down 0.2 2 a f sample = 225ksps 2.8 4.2 only adc on, external reference f sample = 100ksps 2.6 analog positive-supply current a idd all dacs on, no load, internal reference 1.5 4.0 ma ref1 positive-supply rejection psrr av dd = 2.7v -77 db dac positive-supply rejection psrd output code = fffhex, av dd = 2.7v to 5.25v ?.1 ?.5 mv
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports _______________________________________________________________________________________ 7 electrical characteristics (continued) (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) parameter symbol conditions min typ max units adc positive-supply rejection psra full-scale input, av dd = 2.7v to 5.25v ?.06 ?.5 mv timing characteristics (figures 6?3) sclk clock period t cp 40 ns sclk pulse-width high t ch 40/60 duty cycle 16 ns sclk pulse-width low t cl 60/40 duty cycle 16 ns gpio output rise/fall after cs rise t god c load = 20pf 100 ns gpio input setup before cs fall t gsu 0ns ldac pulse width t ldacpwl 20 ns c load = 20pf, slow = 0 1.8 12.0 sclk fall to dout transition (note 16) t dot c load = 20pf, slow = 1 10 40 ns c load = 20pf, slow = 0 1.8 12.0 sclk rise to dout transition (notes 16, 17) t dot c load = 20pf, slow = 1 10 40 ns cs fall to sclk fall setup time t css 10 ns sclk fall to cs rise setup time t csh 0 2000 ns din to sclk fall setup time t ds 10 ns din to sclk fall hold time t dh 0ns cs pulse-width high t cspwh 50 ns cs rise to dout disable t dod c load = 20pf 25 ns cs fall to dout enable t doe c load = 20pf 1.5 25.0 ns eoc fall to cs fall t rds 30 ns cksel = 01 (temp sense) or cksel = 10 (temp sense), internal reference on 65 cksel = 01 (temp sense) or cksel = 10 (temp sense), internal reference initially off 140 cksel = 01 (voltage conversion) 9 cksel = 10 (voltage conversion), internal reference on 9 cs or cnvst rise to eoc fall?nternally clocked conversion time t dov cksel = 10 (voltage conversion), internal reference initially off 80 ? cksel = 00, cksel = 01 (temp sense) 40 ns cnvst pulse width t csw cksel = 01 (voltage conversion) 1.4 ?
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 8 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = 2.7v to 5.25v, external reference v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), t a = -40? to +85?, unless other- wise noted. typical values are at av dd = dv dd = 3v. t a = +25?. outputs are unloaded, unless otherwise noted.) note 1: tested at dv dd = av dd = +2.7v. note 2: offset nulled. note 3: no bus activity during conversion. conversion time is defined as the number of conversion clock cycles, multiplied by the clock period. note 4: see table 5 for reference-mode details. note 5: not production tested. guaranteed by design. note 6: see the adc/dac references section. note 7: fast automated test, excludes self-heating effects. note 8: specified over the -40? to +85? temperature range. note 9: refsel[1:0] = 00 or when dacs are not powered up. note 10: dac linearity, gain, and offset measurements are made between codes 115 and 3981. note 11: the dac buffers are guaranteed by design to be stable with a 1nf load. note 12: time required by the dac output to power up and settle within 1 lsb in the external reference mode. note 13: all dac dynamic specifications are valid for a load of 100pf and 10k . note 14: only one digital output (either dout, eoc , or the gpios) can be indefinitely shorted to either supply at one time. note 15: all digital inputs at either dv dd or dgnd. dv dd should not exceed av dd . note 16: see the reset register section and table 9 for details on programming the slow bit. note 17: clock mode 11 only. typical operating characteristics (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) 0 0.1 0.3 0.2 0.4 0.5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 analog shutdown current vs. analog supply voltage max1221 toc01 supply voltage (v) analog shutdown current ( a) analog shutdown current vs. temperature max1221 toc02 temperature ( c) analog shutdown current ( a) 60 35 10 -15 0.1 0.2 0.3 0.4 0 -40 85 adc integral nonlinearity vs. output code max1221 toc03 output code integral nonlinearity (lsb) 3072 2048 1024 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 4096 av dd = dv dd = 5v external reference = 4.096v
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports _______________________________________________________________________________________ 9 typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) adc integral nonlinearity vs. output code max1221 toc04 output code integral nonlinearity (lsb) 3072 2048 1024 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 4096 adc differential nonlinearity vs. output code max1221 toc05 output code differential nonlinearity (lsb) 3072 2048 1024 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 4096 av dd = dv dd = 5v external reference = 4.096v adc differential nonlinearity vs. output code max1221 toc06 output code differential nonlinearity (lsb) 3072 2048 1024 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 4096 0 0.2 0.6 0.4 0.8 1.0 2.5 3.5 3.0 4.0 4.5 5.0 5.5 adc offset error vs. analog supply voltage max1221 toc07 supply voltage (v) offset error (lsb) adc offset error vs. temperature max1221 toc08 temperature ( c) offset error (lsb) 60 35 10 -15 -1 0 1 2 -2 -40 85 1.0 0.5 0 -0.5 -1.0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 adc gain error vs. analog supply voltage max1221 toc09 supply voltage (v) gain error (lsb) adc gain error vs. temperature max1221 toc10 temperature ( c) gain error (lsb) 60 35 10 -15 -1 0 1 2 -2 -40 85 adc external reference input current vs. sampling rate max1221 toc11 sampling rate (ksps) adc external reference input current ( a) 250 200 150 100 50 10 20 30 40 50 60 0 0 300 analog supply current vs. sampling rate max1221 toc12 sampling rate (ksps) analog supply current (ma) 250 200 150 100 50 0.5 1.0 1.5 2.0 2.5 3.0 0 0 300
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 10 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) 1.90 1.94 1.92 1.98 1.96 2.02 2.00 2.04 2.5 3.5 4.0 3.0 4.5 5.0 5.5 analog supply current vs. analog supply voltage max1221 toc13 supply voltage (v) supply current (ma) 1.88 1.92 1.90 1.96 1.94 2.00 1.98 2.02 -40 10 -15 35 60 85 analog supply current vs. temperature max1221 toc14 temperature ( c) analog supply current (ma) av dd = dv dd = 5v av dd = dv dd = 3v dac integral nonlinearity vs. output code max1221 toc15 output code integral nonlinearity (lsb) 3072 2048 1024 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 0 4096 av dd = dv dd = 5v external reference = 4.096v dac integral nonlinearity vs. output code max1221 toc16 output code integral nonlinearity (lsb) 3072 2048 1024 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 0 4096 dac differential nonlinearity vs. output code max1221 toc17 output code differential nonlinearity (lsb) 2059 2056 2053 2050 -0.2 0 0.2 0.4 -0.4 2047 2062 av dd = dv dd = 5v external reference = 4.096v dac differential nonlinearity vs. output code max1221 toc18 output code differential nonlinearity (lsb) 2059 2056 2053 2050 -0.2 0 0.2 0.4 -0.4 2047 2062 0.2 0.4 0.8 0.6 1.0 1.2 2.5 3.5 3.0 4.0 4.5 5.0 5.5 dac full-scale error vs. analog supply voltage max1221 toc19 supply voltage (v) dac full-scale error (lsb) -6 -4 -2 0 2 4 6 8 10 -40 -15 10 35 60 85 dac full-scale error vs. temperature max1221 toc20 temperature ( c) dac full-scale error (lsb) external reference = 4.096v av dd = dv dd = 5v -6 -4 -2 0 2 4 6 8 10 -40 -15 10 35 60 85 dac full-scale error vs. temperature max1221 toc21 temperature ( c) dac full-scale error (lsb) external reference = 2.5v av dd = dv dd = 3v internal reference
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 11 typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) dac full-scale error vs. reference voltage max1221 toc22 reference voltage (v) dac full-scale error (lsb) 4 3 1 2 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 05 av dd = dv dd = 5v dac full-scale error vs. reference voltage max1221 toc23 reference voltage (v) dac full-scale error (lsb) 2.0 2.5 1.5 0.5 1.0 -6 -5 -4 -3 -2 -1 0 -7 0 3.0 dac full-scale error vs. load current max1221 toc24 load current (ma) dac full-scale error (lsb) 25 20 15 10 5 -10 -5 0 5 -15 030 av dd = dv dd = 5v external reference = 4.096v dac full-scale error vs. load current max1221 toc25 load current (ma) dac full-scale error (lsb) 2.5 2.0 1.5 1.0 0.5 -10 -5 0 5 -15 0 3.0 internal reference voltage vs. temperature max1221 toc26 temperature ( c) internal reference voltage (v) 60 35 10 -15 2.49 2.50 2.51 2.52 2.48 -40 85 25.1 25.0 24.9 24.8 24.7 2.5 4.0 3.0 3.5 4.5 5.0 5.5 adc reference supply current vs. analog supply voltage max1221 toc27 supply voltage (v) adc reference supply current ( a) 40.5 40.6 40.8 40.7 40.9 41.0 -40 10 -15 35 60 85 adc reference supply current vs. temperature max1221 toc28 temperature ( c) adc reference supply current ( a) av dd = dv dd = 5v external reference = 4.096v adc reference supply current vs. temperature max1221 toc29 temperature ( c) adc reference supply current ( a) 60 35 10 -15 24.8 24.9 25.0 25.1 24.7 -40 85 av dd = dv dd = 3v external reference = 2.5v adc fft plot max1221 toc30 analog input frequency (khz) amplitude (db) 150 100 50 -140 -120 -100 -80 -60 -40 -20 0 -160 0 200 f sample = 32.768khz f analog_)n = 10.080khz f clk = 5.24288mhz sinad = 71.27dbc snr = 71.45dbc thd = 85.32dbc sfdr = 87.25dbc
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 12 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) adc imd plot max1221 toc31 analog input frequency (khz) amplitude (db) 150 100 50 -140 -120 -100 -80 -60 -40 -20 0 -160 0 200 f clk = 5.24288mhz f in1 = 9.0khz f in2 = 11.0khz a in = -6dbfs imd = 82.99dbc adc crosstalk plot max1221 toc32 analog input frequency (khz) amplitude (db) 150 100 50 -140 -120 -100 -80 -60 -40 -20 0 -160 0 200 f clk = 5.24288mhz f in1 = 10.080khz f in2 = 8.0801khz snr = 72.00dbc thd = 85.24dbc enob = 11.65 bits dac output load regulation vs. output current max1221 toc33 output current (ma) dac output voltage (v) 60 30 0 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.00 -30 90 dac output = midscale sinking sourcing av dd = dv dd = 5v external reference = 4.096v dac output load regulation vs. output current max1221 toc34 output current (ma) dac output voltage (v) 20 10 0 -20 -10 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.21 -30 30 dac output = midscale sinking sourcing gpio output voltage vs. source current max1221 toc35 source current (ma) gpio output voltage (v) 80 60 40 20 1 2 3 4 5 0 0 100 gpioa0, agpioa1 outputs gpioc0, gpioc1 outputs av dd = dv dd = 5v external reference = 4.096v gpio output voltage vs. source current max1221 toc36 source current (ma) gpio output voltage (v) 80 60 40 20 0.5 1.0 1.5 2.0 2.5 3.0 0 0 100 gpioa0, gpioa1 outputs gpioc0, gpioc1 outputs gpio output voltage vs. sink current max1221 toc37 sink current (ma) gpio output voltage (mv) 80 60 40 20 300 600 900 1200 1500 0 0 100 gpioa0, gpioa1 outputs gpioc0, gpioc1 outputs av dd = dv dd = 5v external reference = 4.096v
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 13 typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) gpio output voltage vs. sink current max1221 toc38 sink current (ma) gpio output voltage (mv) 40 50 30 20 10 300 600 900 1200 1500 0 060 gpioa0, gpioa1 outputs gpioc0, gpioc1 outputs temperature sensor error vs. temperature max1221 toc39 temperature ( c) temperature sensor error ( c) 60 35 -15 10 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 -40 85 dac-to-dac crosstalk (r load = 10k , c load = 100pf) max1221 toc40 100 s/div v outa 1v/div v outb 10mv/div ac-coupled dac-to-dac crosstalk (r load = 10k , c load = 100pf) max1221 toc41 100 s/div v outa 2v/div v outb 10mv/div ac-coupled av dd = dv dd = 5v external reference = 4.096v dynamic response rise time (r load = 10k , c load = 100pf) max1221 toc42 1 s/div v out 1v/div cs 1v/div dynamic response rise time (r load = 10k , c load = 100pf) max1221 toc43 1 s/div v out 2v/div cs 2v/div av dd = dv dd = 5v external reference = 4.096v
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 14 ______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) dac digital feedthrough (r load = 10k , c load = 100pf, cs = high, din = low) max1221 toc49 200ns/div v out 100mv/div ac-coupled sclk 2v/div av dd = dv dd = 5v external reference = 4.096v dynamic response fall time (r load = 10k , c load = 100pf) max1221 toc44 1 s/div v out 1v/div cs 1v/div dynamic response fall time (r load = 10k , c load = 100pf) max1221 toc45 1 s/div v out 2v/div cs 2v/div av dd = dv dd = 5v external reference = 4.096v major carry transition (r load = 10k , c load = 100pf) max1221 toc46 1 s/div v out 10mv/div ac-coupled cs 1v/div major carry transition (r load = 10k , c load = 100pf) max1221 toc47 1 s/div v out 20mv/div ac-coupled cs 2v/div av dd = dv dd = 5v external reference = 4.096v dac digital feedthrough (r load = 10k , c load = 100pf, cs = high, din = low) max1221 toc48 200ns/div v out 100mv/div ac-coupled sclk 1v/div
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 15 typical operating characteristics (continued) (av dd = dv dd = 3v external v ref = 2.5v, f clk = 3.6mhz (50% duty cycle), f sample = 225ksps, c load = 50pf, 0.1? capacitor at ref, t a = +25?, unless otherwise noted.) negative full-scale settling time (r load = 10k , c load = 100pf) max1340 toc50 1 s/div v out 1v/div v ldac 1v/div negative full-scale settling time (r load = 10k , c load = 100pf) max1221 toc51 2 s/div v out_ 2v/div v ldac 2v/div av dd = dv dd = 5v external reference = 4.096v positive full-scale settling time (r load = 10k , c load = 100pf) max1221 toc52 1 s/div v out_ 1v/div v ldac 1v/div positive full-scale settling time (r load = 10k , c load = 100pf) max1221 toc53 1 s/div v out_ 2v/div v ldac 2v/div av dd = dv dd = 5v external reference = 4.096v adc reference feedthrough (r load = 10k , c load = 100pf) max1221 toc54 200 s/div v dac-out 10mv/div ac-coupled v ref2 1v/div adc reference switching adc reference feedthrough (r load = 10k , c load = 100pf) max1221 toc55 200 s/div v dac-out 2mv/div ac-coupled v ref2 2v/div av dd = dv dd = 5v external reference = 4.096v adc reference switching
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 16 ______________________________________________________________________________________ pin description pin max1221 MAX1223 max1343 name function 1, 2 1, 2 gpioa0, gpioa1 general-purpose i/o a0, a1. gpioa0, a1 can sink and source 15ma. ? cnvst /ain11 active-low conversion-start input/analog input 11. see table 5 for details on programming the setup register. 333 eoc active-low end-of-conversion output. data is valid after the falling edge of eoc . 444 dv dd digital positive-power input. bypass dv dd to dgnd with a 0.1? capacitor. 5 5 5 dgnd digital ground. connect dgnd to agnd. 6 6 6 dout serial-data output. data is clocked out on the falling edge of the sclk clock in modes 00, 01, and 10. data is clocked out on the rising edge of the sclk clock in mode 11. it is high impedance when cs is high. 7 7 7 sclk serial-clock input. clocks data in and out of the serial interface. (duty cycle must be 40% to 60%). see table 5 for details on programming the clock mode. 8 8 8 din serial-data input. din data is latched into the serial interface on the falling edge of sclk. 9?2 out0?ut3 dac outputs 9?2, 16?9 9?2, 16?9 out0?ut7 dac outputs 13 13 13 av dd positive analog power input. bypass av dd to agnd with a 0.1? capacitor. 14 14 14 agnd analog ground 15, 23, 32, 33 2, 15, 24, 32 15, 23, 32, 33 n.c. no connection. not internally connected. 16?9 d.c. do not connect. do not connect to this pin. 20 20 20 ldac active-low load dac. ldac is an asynchronous active-low input that updates the dac outputs. drive ldac low to make the dac registers transparent. 21 21 21 cs active-low chip-select input. when cs is low, the serial interface is enabled. when cs is high, dout is high impedance. 22 22 22 res_sel reset select. select dac wake-up mode. set res_sel low to wake up the dac outputs with a 100k resistor to gnd or set res_sel high to wake up the dac outputs with a 100k resistor to v ref . the default is the external v ref . 24, 25 24, 25 gpioc0, gpioc1 general-purpose i/o c0, c1. gpioc0, c1 can sink 4ma and source 2ma.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 17 pin description (continued) pin max1221 MAX1223 max1343 name function 23, 25, 27?1, 33, 34, 35 ain0?in9 analog inputs 26 26 26 ref1 reference 1 input. reference voltage; leave unconnected to use the internal reference (2.5v). ref1 is the positive reference in adc differential mode. bypass ref1 to agnd with a 0.1? capacitor in external reference mode only. see the adc/dac references section. 27?1, 34 27?1, 34 ain0?in5 analog inputs 35 35 ref2/ain6 reference 2 input/analog input channel 6. see table 5 for details on programming the setup register. 36 36 cnvst /ain7 active-low conversion-start input/analog input 7. see table 5 for details on programming the setup register. 36 ref2/ain10 reference 2 input/analog input channel 10. see table 5 for details on programming the setup register. ep exposed pad. must be externally connected to agnd. do not use as a ground connect.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 18 ______________________________________________________________________________________ detailed description the max1221/MAX1223/max1343 integrate a multi- channel 12-bit adc, and an octal/quad 12-bit dac in a single ic. the devices also include a temperature sen- sor and configurable gpios with a 25mhz spi-/qspi-/ microwire-compatible serial interface. the adc is available in a 12 or an eight input-channel version. the dac outputs settle within 2.0?, and the adc has a 225ksps conversion rate. all devices include an internal reference (2.5v) provid- ing a well-regulated, low-noise reference for both the adc and dac. programmable reference modes for the adc and dac allow the use of an internal reference, an external reference, or a combination of both. features such as an internal ?? accurate temperature sensor, fifo, scan modes, programmable internal or external clock modes, data averaging, and autoshutdown allow users to minimize both power consumption and proces- sor requirements. the low glitch energy (4nv s) and low digital feedthrough (0.5nv s) of the integrated dacs make these devices ideal for digital control of fast-response closed-loop systems. the devices are guaranteed to operate with a supply voltage from +2.7v to +5.25v. the devices consume 2.5ma at 225ksps throughput, only 22? at 1ksps throughput, and under 0.2? in the shutdown mode. the max1221/max1343 offer four gpios that can be configured as inputs or outputs. figure 1 shows the max1221 functional diagram. the max1221/max1343 only include the gpioa0, gpioa1 and gpioc0, gpioc1 blocks. the MAX1223 excludes the gpios. the output-conditioning circuitry takes the internal parallel data bus and converts it to a serial data format at dout, with the appropriate wake-up timing. the arithmetic logic unit (alu) performs the averaging function. spi-compatible serial interface the max1221/MAX1223/max1343 feature a serial inter- face that is compatible with spi and microwire devices. for spi, ensure the spi bus master (typically a microcontroller (?)) runs in master mode so that it generates the serial clock signal. select the sclk fre- quency of 25mhz or less, and set the clock polarity (cpol) and phase (cpha) in the ? control registers to the same value. the max1221/MAX1223/max1343 operate with sclk idling high or low, and thus operate with cpol = cpha = 0 or cpol = cpha = 1. set cs low to latch any input data at din on the falling edge of sclk. output data at dout is updated on the falling edge of sclk in clock modes 00, 01, and 10. output data at dout is updated on the rising edge of sclk in clock mode 11. see figures 6?1. bipolar true-differen- tial results and temperature-sensor results are available in two? complement format, while all other results are in binary. a high-to-low transition on cs initiates the data-input operation. serial communications to the adc always begin with an 8-bit command byte (msb first) loaded from din. the command byte and the subsequent data bytes are clocked from din into the serial interface on the falling edge of sclk. the serial-interface and fast- interface circuitry is common to the adc, dac, and gpio sections. the content of the command byte determines whether the spi port should expect 8, 16, or 24 bits and whether the data is intended for the adc, dac, or gpios (if applicable). see table 1. driving cs high resets the serial interface. the conversion register controls adc channel selec- tion, adc scan mode, and temperature-measurement requests. see table 4 for information on writing to the conversion register. the setup register controls the clock mode, reference, and unipolar/bipolar adc con- figuration. use a second byte, following the first, to write to the unipolar-mode or bipolar-mode registers. see table 5 for details of the setup register and see tables 6, 7, and 8 for setting the unipolar- and bipolar- mode registers. hold cs low between the command byte and the second and third byte. the adc averag- ing register is specific to the adc. see table 9 to address that register. table 11 shows the details of the reset register. begin a write to the dac by writing 0001xxxx as a command byte. the last 4 bits of this command byte are don?-care bits. write another 2 bytes (holding cs low) to the dac interface register following the com- mand byte to select the appropriate dac and the data to be written to it. see the dac serial interface section and tables 10, 17, and 18. write to the gpios (if applicable) by issuing a command byte to the appropriate register. writing to the max1221/max1343 gpios requires 1 additional byte fol- lowing the command byte. see tables 12?6 for details on gpio configuration, writes, and reads. see the gpio command section. command bytes written to the gpios on devices without gpios are ignored.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 19 dout eoc address ain0 ain5 ref2/ ain6 cnvst/ ain7 ref1 din sclk cs gpioa0, gpioa1 gpioc0, gpioc1 av dd spi port gpio control input register dac register output conditioning 12-bit dac buffer user-programmable i/o oscillator out0 out1 out2 out4 out5 out6 max1221 12-bit sar adc logic control temperature sensor fifo and alu ldac res_sel agnd t/h ref2 input register dac register output conditioning 12-bit dac buffer input register dac register output conditioning 12-bit dac buffer input register dac register output conditioning 12-bit dac buffer input register internal reference dac register output conditioning 12-bit dac buffer input register dac register output conditioning 12-bit dac buffer input register dac register output conditioning 12-bit dac buffer input register dac register output conditioning 12-bit dac buffer out3 out7 dgnd dv dd cnvst figure 1. max1221 functional diagram
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 20 ______________________________________________________________________________________ table 1. command byte (msb first) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 conversion 1 chsel3 chsel2 chsel1 chsel0 scan1 scan0 temp setup 0 1 cksel1 cksel0 refsel1 refsel0 diffsel1 diffsel0 adc averaging 0 0 1 avgon navg1 navg0 nscan1 nscan0 dac select 0 0 0 1 xxxx reset 0 0 0 0 1 reset slow fbgon gpio configure* 0 0 000011 gpio write* 0 0 000010 gpio read* 0 0 000001 no operation 0 0 000000 x = don? care. * only applicable on the max1221/max1343. power-up default state the max1221/MAX1223/max1343 power up with all blocks in shutdown (including the reference). all regis- ters power up in state 00000000, except for the setup register and the dac input register. the setup register powers up at 0010 1000 with cksel1 = 1 and ref- sel1 = 1. the dac input register powers up to fffh when res_sel is high and powers up to 000h when res_sel is low. 12-bit adc the max1221/MAX1223/max1343 adcs use a fully dif- ferential successive-approximation register (sar) con- version technique and on-chip track-and-hold (t/h) circuitry to convert temperature and voltage signals into 12-bit digital results. the analog inputs accept both sin- gle-ended and differential input signals. single-ended signals are converted using a unipolar transfer function, and differential signals are converted using a selec- table bipolar or unipolar transfer function. see the adc transfer functions section for more data. adc clock modes when addressing the setup, register bits 5 and 4 of the command byte (cksel1 and cksel0, respectively) control the adc clock modes. see table 5. choose between four different clock modes for various ways to start a conversion and determine whether the acquisi- tions are internally or externally timed. select clock mode 00 to configure cnvst /ain_ to act as a conver- sion start and use it to request internally timed conver- sions, without tying up the serial bus. in clock mode 01, use cnvst to request conversions one channel at a time, thereby controlling the sampling speed without tying up the serial bus. request and start internally timed conversions through the serial interface by writ- ing to the conversion register in the default clock mode, 10. use clock mode 11 with sclk up to 3.6mhz for externally timed acquisitions to achieve sampling rates up to 225ksps. clock mode 11 disables scanning and averaging. see figures 6? for timing specifications on how to begin a conversion. these devices feature an active-low, end-of-conversion output. eoc goes low when the adc completes the last requested operation and is waiting for the next com- mand byte. eoc goes high when cs or cnvst go low. eoc is always high in clock mode 11. single-ended or differential conversions the max1221/MAX1223/max1343 use a fully differen- tial adc for all conversions. when a pair of inputs are connected as a differential pair, each input is connect- ed to the adc. when configured in single-ended mode, the positive input is the single-ended channel and the negative input is referred to agnd. see figure 2. in differential mode, the t/h samples the difference between two analog inputs, eliminating common-mode dc offsets and noise. in+ and in- are selected from the following pairs: ain0/ain1, ain2/ain3, ain4/ain5, ain6/ain7, ain8/ain9, ain10/ain11. ain0?in7 are available on all devices. ain0?in11 are available on the MAX1223. see tables 5? for more details on con- figuring the inputs. for the inputs that are configurable as cnvst , ref2, and an analog input, only one func- tion can be used at a time. unipolar or bipolar conversions address the unipolar- and bipolar-mode registers through the setup register (bits 1 and 0). see table 5 for
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 21 the setup register. see figures 3 and 4 for the transfer- function graphs. program a pair of analog inputs for dif- ferential operation by writing a one to the appropriate bit of the bipolar- or unipolar-mode register. unipolar mode sets the differential input range from 0 to v ref1. a nega- tive differential analog input in unipolar mode causes the digital output code to be zero. selecting bipolar mode sets the differential input range to ? ref1 / 2. the digital output code is binary in unipolar mode and two? com- plement in bipolar mode. in single-ended mode, the max1221/MAX1223/ max1343 always operate in unipolar mode. the analog inputs are internally referenced to agnd with a full-scale input range from 0 to the selected reference voltage. analog input (t/h) the equivalent circuit of figure 2 shows the adc input architecture of the MAX1223. in track mode, a positive input capacitor is connected to ain0?in11 in single- ended mode and ain0, ain2, ain4?in10 in differential mode. a negative input capacitor is connected to agnd in single-ended mode or ain1, ain3, ain5?in11 in dif- ferential mode. the max1221/max1343 feature eight analog input channels (ain0?in7). in track mode, a pos- itive input capacitor is connected to ain0?in7 in single- ended mode and to ain0, ain2, ain4, and ain6 in differential mode. a negative input capacitor is connected to agnd in single-ended mode or to ain1, ain3, ain5, and ain7 in differential mode. for external t/h timing, use clock mode 01. after the t/h enters hold mode, the differ- ence between the sampled positive and negative input voltages is converted. the input capacitance charging rate determines the time required for the t/h to acquire an input signal. if the input signal? source impedance is high, the required acquisition time lengthens. any source impedance below 300 does not signifi- cantly affect the adc? ac performance. a high-imped- ance source can be accommodated either by lengthening t acq (only in clock mode 01) or by placing a 1? capacitor between the positive and negative ana- log inputs. the combination of the analog-input source impedance and the capacitance at the analog input cre- ates an rc filter that limits the analog input bandwidth. input bandwidth the adc? input-tracking circuitry has a 1mhz small-sig- nal bandwidth, making it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. analog input protection internal electrostatic-discharge (esd) protection diodes clamp all analog inputs to av dd and agnd, allowing the inputs to swing from (agnd - 0.3v) to (av dd + 0.3v) without damage. however, for accurate conver- sions near full scale, the inputs must not exceed av dd by more than 50mv or be lower than agnd by 50mv. if an analog input voltage exceeds the supplies, limit the input current to 2ma. internal fifo the max1221/MAX1223/max1343 contain a first- in/first-out (fifo) buffer that holds up to 16 adc results plus one temperature result. the internal fifo allows the adc to process and store multiple internally clocked conversions and a temperature measurement without being serviced by the serial bus. if the fifo is filled and further conversions are request- ed without reading from the fifo, the oldest adc results are overwritten by the new adc results. each result contains 2 bytes, with the msb preceded by four leading zeros. after each falling edge of cs , the oldest available pair of bytes of data is available at dout, msb first. when the fifo is empty, dout is zero. the first 2 bytes of data read out after a temperature measurement always contain the 12-bit temperature result, preceded by four leading zeros, msb first. if anoth- er temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. temperature results are in degrees celsius (two? complement), at a resolution of 8 ain0?in11 (single-ended), ain0, ain2, ain4?in10 (differential) comparator hold acq acq hold acq hold av dd / 2 ref1 agnd cin+ cin- dac agnd (single-ended), ain1, ain3, ain5?in11 (differential) figure 2. MAX1223 equivalent input circuit
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 22 ______________________________________________________________________________________ lsb per degree. see the temperature measurements section for details on converting the digital code to a tem- perature. 12-bit dac in addition to the 12-bit adc, the max1221/MAX1223/ max1343 also include eight (max1221/MAX1223) or four (max1343) voltage-output, 12-bit, monotonic dacs with less than 4 lsb integral nonlinearity error and less than 1 lsb differential nonlinearity error. each dac has a 2s settling time and ultra-low glitch energy (4nv s). the 12-bit dac code is unipolar binary with 1 lsb = v ref / 4096. dac digital interface figure 1 shows the functional diagram of the max1221. the shift register converts a serial 16-bit word to parallel data for each input register operating with a clock rate up to 25mhz. the spi-compatible digital interface to the shift register consists of cs , sclk, din, and dout. serial data at din is loaded on the falling edge of sclk. pull cs low to begin a write sequence. begin a write to the dac by writing 0001xxxx as a command byte. the last 4 bits of the dac select register are don?-care bits. see table 10. write another 2 bytes to the dac inter- face register following the command byte to select the appropriate dac and the data to be written to it. see tables 17 and 18. the double-buffered dacs include an input and a dac register. the input registers are directly connected to the shift register and hold the result of the most recent write operation. the 12-bit dac registers hold the current out- put code for the respective dac. data can be transferred from the input registers to the dac registers by pulling ldac low or by writing the appropriate dac command sequence at din. see table 17. the outputs of the dacs are buffered through eight (max1221/MAX1223) or four (max1343) rail-to-rail op amps. the max1221/MAX1223/max1343 dac output-voltage range is based on the internal reference or an external reference. write to the setup register (see table 5) to program the reference. if using an external voltage reference, bypass ref1 with a 0.1? capacitor to agnd. the internal reference is 2.5v. when using an external reference on any of these devices, the voltage range is 0.7v to av dd . dac transfer function see table 2 for various analog outputs from the dac. dac power-on wake-up modes the state of the res_sel input determines the wake-up state of the dac outputs. connect res_sel to av dd or agnd upon power-up to be sure the dac outputs wake up to a known state. connect res_sel to agnd to wake up all dac outputs at 000h. while res_sel is low, the 100k internal resistor pulls the dac outputs to agnd and the output buffers are powered down. connect res_sel to av dd to wake up all dac outputs at fffh. while res_sel is high, the 100k pullup resistor pulls the dac outputs to v ref1 and the output buffers are powered down. dac power-up modes see table 18 for a description of the dac power-up and power-down modes. gpios in addition to the internal adc and dac, the max1221/max1343 also provide four gpio channels, gpioa0, gpioa1, gpioc0, gpioc1. read and write to the gpios as detailed in table 1 and tables 12?6. also, see the gpio command section. see figures 11 and 12 for gpio timing. write to the gpios by writing a command byte to the gpio command register. write a single data byte to the max1221/max1343 following the command byte. the gpios can sink and source current. gpioa0 and gpioa1 can sink and source up to 15ma. gpioc0 and gpioc1 can sink 4ma and source 2ma. see table 3. dac contents msb lsb analog output 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 0111 0111 0000 0000 0001 0000 0000 0000 0 + ? ? ? ? ? ? v ref 4095 4096 + ? ? ? ? ? ? = + ? ? ? ? ? ? v v ref ref 2048 4096 2 + ? ? ? ? ? ? v ref 2047 4096 + ? ? ? ? ? ? v ref 1 4096 + ? ? ? ? ? ? v ref 2049 4096 table 2. dac output code table
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 23 clock modes internal clock the max1221/MAX1223/max1343 can operate from an internal oscillator. the internal oscillator is active in clock modes 00, 01, and 10. figures 6, 7, and 8 show how to start an adc conversion in the three internally timed conversion modes. read out the data at clock speeds up to 25mhz through the spi interface. external clock set cksel1 and cksel0 in the setup register to 11 to set up the interface for external clock mode 11. see table 5. pulse sclk at speeds from 0.1mhz to 3.6mhz. write to sclk with a 40% to 60% duty cycle. the sclk frequency controls the conversion timing. see figure 9 for clock mode 11 timing. see the adc conversions in clock mode 11 section. adc/dac references address the reference through the setup register, bits 3 and 2. see table 5. following a wake-up delay, set refsel[1:0] = 00 to program both the adc and dac for internal reference use. set refsel[1:0] = 10 to pro- gram the adc for internal reference use without a wake-up delay. set refsel[1:0] = 10 to program the dac for external reference, ref1. when using ref1 or ref2/ain_ in external-reference mode, connect a 0.1? capacitor to agnd. set refsel[1:0] = 01 to program the adc and dac for external-reference mode. the dac uses ref1 as its external reference, while the adc uses ref2 as its external reference. set refsel[1:0] = 11 to program the adc for external dif- ferential reference mode. ref1 is the positive reference and ref2 is the negative reference in the adc external differential mode. when refsel[1:0] = 00 or 10, ref2/ain_ functions as an analog input channel. when refsel[1:0] = 01 or 11, ref2/ain_ functions as the device? negative reference. temperature measurements issue a command byte setting bit 0 of the conversion register to one to take a temperature measurement. see table 4. the max1221/MAX1223/max1343 perform temperature measurements with an internal diode-con- nected transistor. the diode bias current changes from 68? to 4? to produce a temperature-dependent bias voltage difference. the second conversion result at 4? is subtracted from the first at 68? to calculate a digital value that is proportional to absolute temperature. the output data appearing at dout is the digital code above, minus an offset to adjust from kelvin to celsius. the reference voltage used for the temperature mea- surements is always derived from the internal reference source to ensure that 1 lsb corresponds to 1/8 of a degree celsius. on every scan where a temperature measurement is requested, the temperature conversion is carried out first. the first 2 bytes of data read from the fifo contain the result of the temperature measure- ment. if another temperature measurement is per- formed before the first temperature result is read out, the old measurement is overwritten by the new result. temperature results are in degrees celsius (two? com- plement). see the applications information section for information on how to perform temperature measure- ments in each clock mode. register descriptions the max1221/MAX1223/max1343 communicate between the internal registers and the external circuitry through the spi-compatible serial interface. table 1 details the command byte, the registers, and the bit names. tables 4?2 show the various functions within the conversion register, setup register, unipolar-mode register, bipolar-mode register, adc averaging regis- ter, dac select register, reset register, and gpio com- mand register, respectively. conversion register select active analog input channels, scan modes, and a single temperature measurement per scan by issuing a command byte to the conversion register. table 4 details channel selection, the four scan modes, and how to request a temperature measurement. start a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the cnvst pin when in clock mode 00 or 01. see figures 6 and 7 for timing specifications for starting a scan with cnvst . a conversion is not performed if it is requested on a channel or one of the channel pairs that has been con- figured as cnvst or ref2. for channels configured as differential pairs, the chsel0 bit is ignored and the two pins are treated as a single differential channel. for the max1221/max1343, t he chsel3 bit must be zero. max1221/max1343 current gpioa0, gpioa1 (ma) gpioc0, gpioc1 (ma) sink 15 4 source 15 2 table 3. gpio maximum sink/source current
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 24 ______________________________________________________________________________________ channels 8?1 are invalid. any scans or averages on these channles can cause corrupt data. select scan mode 00 or 01 to return one result per sin- gle-ended channel and one result per differential pair within the selected scanning range (set by bits 2 and 1, scan1 and scan0), plus one temperature result if selected. select scan mode 10 to scan a single input channel numerous times, depending on nscan1 and nscan0 in the adc averaging register (table 9). select scan mode 11 to return only one result from a single channel. setup register issue a command byte to the setup register to config- ure the clock, reference, power-down modes, and adc single-ended/differential modes. table 5 details the bits in the setup-register command byte. bits 5 and 4 (cksel1 and cksel0) control the clock mode, acqui- sition and sampling, and the conversion start. bits 3 and 2 (refsel1 and refsel0) set the device for either internal or external reference. bits 1 and 0 (diffsel1 and diffsel0) address the adc unipolar-mode and bipolar-mode registers and configure the analog input channels for differential operation. the adc reference is always on if any of the following conditions are true: 1) the fbgon bit is set to one in the reset register. 2) at least one dac output is powered up and refsel[1:0] (in the setup register) = 00. 3) at least one dac is powered down through the 100k to v ref and refsel[1:0] = 00. if any of the above conditions exist, the adc reference is always on, but there is a 188 clock-cycle delay before temperature-sensor measurements begin, if requested. table 4. conversion register* bit name bit function 7 (msb) set to one to select conversion register. chsel3 6 analog input channel select (MAX1223). set to 0 on the max1221/max1343. chsel2 5 analog input channel select. chsel1 4 analog input channel select. chsel0 3 analog input channel select. scan1 2 scan mode select. scan0 1 scan mode select. temp 0 (lsb) set to one to take a single temperature measurement. the first conversion result of a scan contains temperature information. chsel3 chsel2 chsel1 chsel0 selected channel (n) 0 0 0 0 ain0 0 0 0 1 ain1 0 0 1 0 ain2 0 0 1 1 ain3 0 1 0 0 ain4 0 1 0 1 ain5 0 1 1 0 ain6 0 1 1 1 ain7 1 0 0 0 ain8 1 0 0 1 ain9 1 0 1 0 ain10 1 0 1 1 ain11 scan1 scan0 scan mode (channel n is selected by bits chsel3?hsel0) 0 0 scans channels 0 through n. 01 scans channels n through the highest numbered channel. 10 s cans channel n r epeated l y. the ad c aver ag ing reg i ster sets the numb er of r esul ts. 11n o scan. c onver ts channel n once onl y. * see below for bit details.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 25 table 5. setup register* bit name bit function 7 (msb) set to zero to select setup register. 6 set to one to select setup register. cksel1 5 clock mode and cnvst configuration; resets to one at power-up. cksel0 4 clock mode and cnvst configuration. refsel1 3 reference-mode configuration. refsel0 2 reference-mode configuration. diffsel1 1 unipolar-/bipolar-mode register configuration for differential mode. diffsel0 0 (lsb) unipolar-/bipolar-mode register configuration for differential mode. table 5a. clock modes (see clock modes section) cksel1 cksel0 conversion clock acquisition/sampling cnvst configuration 0 0 internal internally timed. cnvst 0 1 internal externally timed by cnvst . cnvst 1 0 internal internally timed. ain11/ain7 1 1 external (3.6mhz max) externally timed by sclk. ain11/ain7 table 5b. clock modes 00, 01, and 10 refsel1 refsel0 voltage reference override conditions autoshutdown ref2 configuration ain inter nal r efer ence tur ns off after scan i s com p l ete. if i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed d el ay of 218 i nter nal - conver si on cl ock cycl es. 00 internal (dac and adc) temperature internal reference required. there is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. ain10/ain6 ain internal reference not used. 01 external single- ended (ref1 for dac and ref2 for adc) temperature internal reference required. there is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. ref2 ain default reference mode. internal reference turns off after scan is complete. if internal reference is turned off, there is a programmed delay of 218 internal- conversion clock cycles. 10 internal (adc) and external ref1 (dac) temperature internal reference required. there is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. ain10/ain6 ain internal reference not used. 11 external differential (adc), external ref1 (dac) temperature internal reference required. there is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up. ref2 * see below for bit details.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 26 ______________________________________________________________________________________ table 5c. clock mode 11 refsel1 refsel0 voltage reference override conditions autoshutdown ref2 configuration ain inter nal r efer ence tur ns off after scan i s com p l ete. if i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed d el ay of 218 exter nal - conver si on cl ock cycl es. 00 internal (dac and adc) temperature inter nal r efer ence r eq ui r ed . ther e i s a p r og r am m ed d el ay of 244 exter nal - conver si on cl ock cycl es for the i nter nal r efer ence. tem p er atur e- sensor outp ut ap p ear s at d ou t after 188 fur ther exter nal cl ock cycl es. ain10/ain6 ain internal reference not used. 01 external single- ended (ref1 for dac and ref2 for adc) tem p er atur e inter nal r efer ence r eq ui r ed . ther e i s a p r og r am m ed d el ay of 244 exter nal - conver si on cl ock cycl es for the i nter nal r efer ence. tem p er atur e- sensor outp ut ap p ear s at d ou t after 188 fur ther exter nal cl ock cycl es. ref2 ain default reference mode. internal reference turns off after scan is complete. if internal reference is turned off, there is a programmed delay of 218 external- conversion clock cycles. 10 internal (adc) and external ref1 (dac) temperature inter nal r efer ence r eq ui r ed . ther e i s a p r og r am m ed d el ay of 244 exter nal - conver si on cl ock cycl es for the i nter nal r efer ence. tem p er atur e- sensor outp ut ap p ear s at d ou t after 188 fur ther exter nal cl ock cycl es. ain10/ain6 ain internal reference not used. 11 external differential (adc), external ref1 (dac) temperature inter nal r efer ence r eq ui r ed . ther e i s a p r og r am m ed d el ay of 244 exter nal - conver si on cl ock cycl es for the i nter nal r efer ence. tem p er atur e- sensor outp ut ap p ear s at d ou t after 188 fur ther exter nal cl ock cycl es. ref2 table 5d. differential select modes diffsel1 diffsel0 function 0 0 no data follows the command setup byte. unipolar-mode and bipolar-mode registers remain unchanged. 0 1 no data follows the command setup byte. unipolar-mode and bipolar-mode registers remain unchanged. 1 0 1 byte of data follows the command setup byte and is written to the unipolar-mode register. 1 1 1 byte of data follows the command setup byte and is written to the bipolar-mode register.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 27 table 6. unipolar-mode register (addressed through the setup register) bit name bit function uch0/1 7 (msb) configure ain0 and ain1 for unipolar differential conversion. uch2/3 6 configure ain2 and ain3 for unipolar differential conversion. uch4/5 5 configure ain4 and ain5 for unipolar differential conversion. uch6/7 4 configure ain6 and ain7 for unipolar differential conversion. uch8/9 3 configure ain8 and ain9 for unipolar differential conversion (MAX1223). set uch8/9 to zero on the max1221/max1343. uch10/11 2 configure ain10 and ain11 for unipolar differential conversion (MAX1223). set uch8/9 to zero on the max1221/max1343. x 1 don? care. x 0 (lsb) don? care. table 7. bipolar-mode register (addressed through the setup register) bit name bit function bch0/1 7 (msb) set to one to configure ain0 and ain1 for bipolar differential conversion. set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure ain0 and ain1 for unipolar single-ended conversion. bch2/3 6 set to one to configure ain2 and ain3 for bipolar differential conversion. set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure ain2 and ain3 for unipolar single-ended conversion. bch4/5 5 set to one to configure ain4 and ain5 for bipolar differential conversion. set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure ain4 and ain5 for unipolar single-ended conversion. bch6/7 4 set to one to configure ain6 and ain7 for bipolar differential conversion. set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure ain6 and ain7 for unipolar single-ended conversion. bch8/9 3 set to one to configure ain8 and ain9 for bipolar differential conversion (MAX1223). set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure ain8 and ain9 for unipolar single-ended conversion. set bch8/9 to zero on the max1221 and max1343. bch10/11 2 set to one to configure ain10 and ain11 for bipolar differential conversion (MAX1223). set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure ain10 and ain11 for unipolar single-ended conversion. set bch8/9 to zero on the max1221 and max1343. x 1 don? care. x 0 (lsb) don? care.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 28 ______________________________________________________________________________________ unipolar/bipolar registers the final 2 bits (lsbs) of the setup register control the unipolar-/bipolar-mode address registers. set diffsel[1:0] = 10 to write to the unipolar-mode regis- ter. set bits diffsel[1:0] = 11 to write to the bipolar- mode register. in both cases, the setup command byte must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register. hold cs low and run 16 sclk cycles before pulling cs high. if the last 2 bits of the setup register are 00 or 01, nei- ther the unipolar-mode register nor the bipolar-mode register is written. any subsequent byte is recognized as a new command byte. see tables 6, 7, and 8 to pro- gram the unipolar- and bipolar-mode registers. both registers power up at all zeros to set the inputs as eight unipolar single-ended channels. to configure a channel pair as single-ended unipolar, bipolar differen- tial, or unipolar differential, see table 8. in unipolar mode, ain+ can exceed ain- by up to v ref . the output format in unipolar mode is binary. in bipolar mode, either input can exceed the other by up to v ref / 2. the output format in bipolar mode is two? complement (see the adc transfer functions section). adc averaging register write a command byte to the adc averaging register to configure the adc to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. table 8. unipolar/bipolar channel function unipolar- mode register bit bipolar-mode register bit channel pair function 0 0 unipolar single-ended 0 1 bipolar differential 1 0 unipolar differential 1 1 unipolar differential table 9. adc averaging register* bit name bit function 7 (msb) set to zero to select adc averaging register. 6 set to zero to select adc averaging register. 5 set to one to select adc averaging register. avgon 4 set to one to turn averaging on. set to zero to turn averaging off. navg1 3 configures the number of conversions for single-channel scans. navg0 2 configures the number of conversions for single-channel scans. nscan1 1 single-channel scan count. (scan mode 10 only.) nscan0 0 (lsb) single-channel scan count. (scan mode 10 only.) avgon navg1 navg0 function 0 x x performs one conversion for each requested result. 1 0 0 performs four conversions and returns the average for each requested result. 1 0 1 performs eight conversions and returns the average for each requested result. 1 1 0 performs 16 conversions and returns the average for each requested result. 1 1 1 performs 32 conversions and returns the average for each requested result. nscan1 nscan0 function (applies only if scan mode 10 is selected) 0 0 scans channel n and returns four results. 0 1 scans channel n and returns eight results. 1 0 scans channel n and returns 12 results. 1 1 scans channel n and returns 16 results. * see below for bit details.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 29 table 9 details the four scan modes available in the adc conversion register. all four scan modes allow averaging as long as the avgon bit, bit 4 in the averaging register, is set to 1. select scan mode 10 to scan the same channel multiple times. clock mode 11 disables averaging. for example, if avgon = 1, navg[1:0] = 00, nscan[1:0] = 11 and scan[1:0] = 10, 16 results are written to the fifo, with each result being the average of four conversions of channel n. dac select register write a command byte 0001xxxx to the dac select register (as shown in table 9) to set up the dac inter- face and indicate that another word will follow. the last 4 bits of the dac select register are don?-care bits. the word that follows the dac select-register command byte controls the dac serial interface. see table 17 and the dac serial interface section. reset register write to the reset register (as shown in table 11) to clear the fifo or reset all registers (excluding the dac and gpio registers) to their default states. when the reset bit in the reset register is set to 0, the fifo is cleared. set the reset bit to one to return all the device registers to their default power-up state. all reg- isters power up in state 00000000, except for the setup register that powers up in clock mode 10 (cksel1 = 1 and refsel1 = 1). the dac and gpio registers are not reset by writing to the reset register. set the slow bit to one to add a 15ns delay in the dout signal path to provide a longer hold time. writing a one to the slow bit also clears the contents of the fifo. set the fbgon bit to one to force the bias block and bandgap reference to power up regardless of the state of the dac and activity of the adc block. setting the fbgon bit high also removes the programmed wake-up delay between conversions in clock modes 01 and 11. setting the fbgon bit high also clears the fifo. table 10. dac select register bit name bit function 7 (msb) set to zero to select dac select register. 6 set to zero to select dac select register. 5 set to zero to select dac select register. 4 set to one to select dac select register. x 3 don? care. x 2 don? care. x 1 don? care. x 0 don? care. table 11. reset register bit name bit function 7 (msb) set to zero to select adc reset register. 6 set to zero to select adc reset register. 5 set to zero to select adc reset register. 4 set to zero to select adc reset register. 3 set to one to select adc reset register. reset 2 set to zero to clear the fifo only. set to one to set the device in its power-on condition. slow 1 set to one to turn on slow mode. fbgon 0 (lsb) set to one to force internal bias block and bandgap reference to be always powered up. table 12. gpio command register bit name bit function 7 (msb) set to zero to select gpio register. 6 set to zero to select gpio register. 5 set to zero to select gpio register. 4 set to zero to select gpio register. 3 set to zero to select gpio register. 2 set to zero to select gpio register. gpiosel1 1 gpio configuration bit. gpiosel2 0 (lsb) gpio write bit. gpiosel1 gpiosel2 function 11 gpio configuration; written data is entered in the gpio configuration register. 10 gpio write; written data is entered in the gpio write register. 01 gpio read; the next 8 sclk cycles transfer the state of all gpio drivers into dout.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 30 ______________________________________________________________________________________ table 13. max1221/max1343 gpio configuration data pin gpio command byte data byte din 0 0 0 0 0 0 1 1 gpioc1 gpioc0 gpioa1 gpioa0 x x x x dout 00000000 0 0 0 0 0000 table 14. max1221/max1343 gpio write data pin gpio command byte data byte din 0 0 0 0 0 0 1 0 gpioc1 gpioc0 gpioa1 gpioa0 x x x x dout 00000000 0 0 0 0 0 0 0 0 gpio command write a command byte to the gpio command register to configure, write, or read the gpios, as detailed in table 12. write the command byte 00000011 to configure the gpios. the eight sclk cycles following the command byte load data from din to the gpio configuration reg- ister in the max1221/max1343. see tables 13 and 14. the register bits are updated after the last cs rising edge. all gpios default to inputs upon power-up. the data in the register controls the function of each gpio, as shown in tables 13, 14, and 16. gpio write write the command byte 00000010 to indicate a gpio write operation. the eight sclk cycles following the com- mand byte load data from din into the gpio write register in the max1221/max1343. see tables 14 and 15. the register bits are updated after the last cs rising edge. gpio read write the command byte 00000001 to indicate a gpio read operation. the eight sclk cycles following the command byte transfer the state of the gpios to dout in the max1221/max1343. see table 16. dac serial interface write a command byte 0001xxxx to the dac select register to indicate the word to follow is written to the dac serial interface, as detailed in tables 1, 10, 17, and 18. write the next 16 bits to the dac interface register, as shown in tables 17 and 18. following the high-to-low transition of cs , the data is shifted synchronously and latched into the input register on each falling edge of sclk. each word is 16 bits. the first 4 bits are the con- trol bits followed by 12 data bits (msb first). see figures 9?2 for dac timing specifications. if cs goes high prior to completing 16 sclk cycles, the command is discarded. to initiate a new transfer, drive cs low again. for example, writing the dac serial interface word 1111 0000 and 0011 0100 disconnects dac outputs 2 and 3 table 15. gpio-mode control configuration bit write bit output state gpio function 1 1 1 output 1 0 0 output 0 1 tri-state input 000 pulldown (open drain) table 16. max1221/max1343 gpio read data pin gpio command byte data byte din 00000001 x x x x x x x x dout 00000000 0 0 0 0 gpioc1 gpioc0 gpioa1 gpioa0
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 31 table 17. dac serial-interface configuration 16-bit serial word msb lsb control bits data bits c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 description function 0000xxxxxxxxxxxx nop no operation. 00010xxxxxxxxxxx reset reset all internal registers to 000h and leave output buffers in their present state. 00011xxxxxxxxxxx pull-high preset all internal registers to fffh and leave output buffers in their present state. 0 0 1 0 dac0 d11?0 to input register 0, dac output unchanged. 0 0 1 1 dac1 d11?0 to input register 1, dac output unchanged. 0 1 0 0 dac2 d11?0 to input register 2, dac output unchanged. 0 1 0 1 dac3 d11?0 to input register 3, dac output unchanged. 0 1 1 0 dac4 d11?0 to input register 4, dac output unchanged (max1221/MAX1223). nop command (max1343). 0 1 1 1 dac5 d11?0 to input register 5, dac output unchanged (max1221/MAX1223). nop command (max1343). 1 0 0 0 dac6 d11?0 to input register 6, dac output unchanged (max1221/MAX1223). nop command (max1343). 1 0 0 1 dac7 d11?0 to input register 7, dac output unchanged (max1221/MAX1223). nop command (max1343). 1 0 1 0 dac0? d11?0 to input registers 0? and dac register 0?. dac outputs updated (write-through). 1 0 1 1 dac4? d11?0 to input registers 4? and dac register 4?. dac outputs updated (write-through) (max1221/MAX1223). nop command (max1343). 1 1 0 0 dac0? d11?0 to input registers 0? and dac register 0? (max1221/MAX1223). d11?0 to input registers 0? and dac registers 0? (max1343). dac outputs updated (write-through).
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 32 ______________________________________________________________________________________ table 18. dac power-up and power-down commands control bits data bits c3 c2 c1 c0 dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 d3 d2 d1 d0 description function 1 1 1 1 0 0 1 x power-up power up individual dac buffers indicated by data in dac0 through dac3. a one indicates the dac output is connected and active. a zero does not affect the dac? present state. 1 1 1 1 0 1 0 x power-down 1 power down individual dac buffers indicated by data in dac0 through dac3. a one indicates the dac output is disconnected and high impedance. a zero does not affect the dac? present state. 1 1 1 1 1 0 0 x power-down 2 power down individual dac buffers indicated by data in dac0 through dac3. a one indicates the dac output is disconnected and pulled to agnd with a 1k resistor. a zero does not affect the dac? present state. 1 1 1 1 0 0 0 x power-down 3 power down individual dac buffers indicated by data in dac0 through dac3. a one indicates the dac output is disconnected and pulled to agnd with a 100k resistor. a zero does not affect the dac? present state. 1 1 1 1 1 1 1 x power-down 4 power down individual dac buffers indicated by data in dac0 through dac3. a one indicates the dac output is disconnected and pulled to ref1 with a 100k resistor. a zero does not affect the dac? present state. table 17. dac serial-interface configuration (continued) 16-bit serial word msb lsb control bits data bits c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 description function 1 1 0 1 dac0? d11?0 to input registers 0? (max1221/MAX1223). d11?0 to input registers 0? (max1343). dac outputs unchanged. 1110 dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 xxxx dac0? input registers to dac registers indicated by ones, dac outputs updated, equivalent to software ldac . (no effect on dacs indicated by zeros.) dac7?ac4 are only valid on the max1221/ MAX1223. these are don?-care bits for the max1343.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 33 and forces them to a high-impedance state. dac out- puts 0 and 1 remain in their previous state. output-data format figures 6? illustrate the conversion timing for the max1221/MAX1223/max1343. all 12-bit conversion results are output in 2-byte format, msb first, with four leading zeros. data appears on dout on the falling edges of sclk. data is binary for unipolar mode and two? complement for bipolar mode and temperature results. see figures 3, 4, and 5 for input/output and temperature-transfer functions. adc transfer functions figure 3 shows the unipolar transfer function for single- ended or differential inputs. figure 4 shows the bipolar transfer function for differential inputs. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = v ref1 / 4096 for unipolar and bipolar operation, and 1 lsb = +0.125? for temperature measurements. bipolar true-differential results and temperature-sensor results are available in two? complement format, while all others are in binary. see tables 6, 7, and 8 for details on which setting (unipolar or bipolar) takes precedence. in unipolar mode, ain+ can exceed ain- by up to v ref1 . in bipolar mode, either input can exceed the other by up to v ref1 / 2. partial reads and partial writes if the first byte of an entry in the fifo is partially read ( cs is pulled high after fewer than eight sclk cycles), the remaining bits are lost for that byte. the next byte of data that is read out contains the next 8 bits. if the first byte of an entry in the fifo is read out fully, but the second byte is read out partially, the rest of that byte is lost. the remaining data in the fifo is unaffected and can be read out normally after taking cs low again, as long as the 4 leading bits (normally zeros) are ignored. if cs is pulled low before eoc goes low, a conversion may not be completed and the fifo data may not be correct. incorrect writes (pulling cs high before com- pleting eight sclk cycles) are ignored and the register remains unchanged. full-scale transition 111....111 0 input voltage (lsb) fs = v ref 111....110 111....101 offset binary output code (lsb) 000....011 000....010 000....001 000....000 2 13 fs 1 lsb = v ref / 4096 fs - 3/2 lsb figure 3. unipolar transfer function?ull scale (fs) = v ref output code 011....111 temperature ( c) 011....110 000....001 111....101 100....001 100....000 111....111 111....110 000....000 0 000....010 -256 +255.5 figure 5. temperature transfer function 011....111 -fs input voltage (lsb) fs = v ref / 2 + v com v ref = v ref+ - v ref- -fs = -v ref / 2 011....110 011....101 000....001 000....000 111....111 offset binary output code (lsb) 100....011 100....010 100....001 100....000 0 (com) -1 +1 +fs - 1 lsb 1 lsb = v ref / 4096 zs = com v ref v ref v ref (com) v ref figure 4. bipolar transfer function?ull scale ( fs) = v ref / 2
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 34 ______________________________________________________________________________________ applications information internally timed acquisitions and conversions using cnvst adc conversions in clock mode 00 in clock mode 00, the wake-up, acquisition, conversion, and shutdown sequence is initiated through cnvst and performed automatically using the internal oscilla- tor. results are added to the internal fifo to be read out later. see figure 6 for clock mode 00 timing after a command byte is issued. see table 5 for details on programming the clock mode in the setup register. initiate a scan by setting cnvst low for at least 40ns before pulling it high again. the max1221/MAX1223/ max1343 then wake up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. wait until eoc goes low before pulling cs low to communicate with the serial interface. eoc stays low until cs or cnvst is pulled low again. a temperature-conversion result, if requested, precedes all other fifo results. do not issue a second cnvst signal before eoc goes low; otherwise, the fifo can be corrupted. wait until all conversions are complete before reading the fifo. spi communications to the dac and gpio registers are per- mitted during conversion. however, coupled noise may result in degraded adc signal-to-noise ratio (snr). (up to 514 internally clocked acquisitions and conversions) cs dout msb1 t rds lsb1 msb2 sclk cnvst eoc figure 6. clock mode 00?fter writing a command byte, set cnvst low for at least 40ns to begin a conversion. (conversion 2) t csw t dov (acquisition 2) (acquisition 1) (conversion 1) cs dout msb1 lsb1 msb2 sclk cnvst eoc figure 7. clock mode 01?fter writing a command byte, request multiple conversions by setting cnvst low for each conversion.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 35 (up to 514 internally clocked acquisitions and conversions) msb1 t dov lsb1 msb2 (conversion byte) cs dout sclk din eoc figure 8. clock mode 10?he command byte to the conversion register begins the acquisition ( cnvst is not required). externally timed acquisitions and internally timed conversions with cnvst adc conversions in clock mode 01 in clock mode 01, conversions are requested one at a time using cnvst and performed automatically using the internal oscillator. see figure 7 for clock mode 01 timing after a command byte is issued. setting cnvst low begins an acquisition, wakes up the adc, and places it in track mode. hold cnvst low for at least 1.4? to complete the acquisition. if reference mode 00 or 10 is selected, an additional 45? is required for the internal reference to power up. if a tem- perature measurement is being requested, reference power-up and temperature measurement is internally timed. in this case, hold cnvst low for at least 40ns. set cnvst high to begin a conversion. sampling is completed approximately 500ns after cnvst goes high. after the conversion is complete, the adc shuts down and pulls eoc low. eoc stays low until cs or cnvst is pulled low again. wait until eoc goes low before pulling cs or cnvst low. the number of cnvst signals must equal the number of conversions requested by the scan and averaging registers to correctly update the fifo. wait until all conversions are complete before reading the fifo. spi communications to the dac and gpio registers are permitted during conversion. however, coupled noise may result in degraded adc snr. if averaging is turned on, multiple cnvst pulses need to be performed before a result is written to the fifo. once the proper number of conversions has been performed to generate an averaged fifo result (as specified to the averaging register), the scan logic automatically switch- es the analog input multiplexer to the next requested channel. if a temperature measurement is programmed, it is performed after the first rising edge of cnvst follow- ing the command byte written to the conversion register. the temperature-conversion result is available on dout once eoc has been pulled low.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 36 ______________________________________________________________________________________ internally timed acquisitions and conversions using the serial interface adc conversions in clock mode 10 in clock mode 10, the wake-up, acquisition, conversion, and shutdown sequence is initiated by writing a com- mand byte to the conversion register, and is performed automatically using the internal oscillator. this is the default clock mode upon power-up. see figure 8 for clock mode 10 timing. initiate a scan by writing a command byte to the conver- sion register. the max1221/MAX1223/max1343 then power up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. if a temperature measurement is requested, the temperature result precedes all other fifo results. eoc stays low until cs is pulled low again. wait until all con- versions are complete before reading the fifo. spi communications to the dac and gpio registers are per- mitted during conversion. however, coupled noise may result in degraded adc snr. externally clocked acquisitions and conversions using the serial interface adc conversions in clock mode 11 in clock mode 11, acquisitions and conversions are ini- tiated by writing a command byte to the conversion register and are performed one at a time using the sclk as the conversion clock. scanning, averaging and the fifo are disabled, and the conversion result is available at dout during the conversion. output data is updated on the rising edge of sclk in clock mode 11. see figure 9 for clock mode 11 timing. initiate a conversion by writing a command byte to the conversion register followed by 16 sclk cycles. if cs is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100?. to continuously convert at 16 cycles per conversion, alternate 1 byte of zeros (nop byte) between each conversion byte. if 2 nop bytes follow a conversion byte, the analog cells power down at the end of the second nop. set the fbgon bit to one in the reset register to keep the inter- nal bias block powered. if reference mode 00 is requested, or if an external refer- ence is selected but a temperature measurement is being requested, wait 45? with cs high after writing the con- version byte to extend the acquisition and allow the inter- nal reference to power up. to perform a temperature measurement, write 24 bytes (192 cycles) of zeros after the conversion byte. the temperature result appears on dout during the last 2 bytes of the 192 cycles. conversion-time calculations the conversion time for each scan is based on a num- ber of different factors: conversion time per sample, samples per result, results per scan, if a temperature measurement is requested, and if the external refer- ence is in use. use the following formula to calculate the total conversion time for an internally timed conver- sion in clock mode 00 and 10 (see the electrical characteristics , as applicable): total conversion time = t cnv x n avg x n scan + t ts + t int-ref,su where: t cnv = t dov (where t dov is dependent from the clock and reference mode selected.) sclk dout msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) din (conversion byte) cs eoc figure 9. clock mode 11?xternally timed acquisition, sampling, and conversion without cnvst
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 37 t csh sclk din dout cs 1234 32 16 8 d15 d14 d13 d12 d11 5 d15 d7 d14 d6 d13 d5 d12 d4 d0 d1 d0 t dod t dot t css t cspwh d1 t doe t ds t dh t ch t cl figure 10. dac/gpio serial-interface timing (clock modes 00, 01, and 10) n avg = samples per result (amount of averaging) n scan = number of times each channel is scanned; set to one unless [scan1, scan0] = 10 t ts = time required for temperature measurement (58.1?); set to zero if temperature measurement is not requested t int-ref,su = t wu (external-reference wake-up); if a conversion using the external reference is requested in clock mode 01, the total conversion time depends on how long cnvst is held low or high. conversion time in externally clocked mode (cksel1, cksel0 = 11) depends on the sclk period and how long cs is held high between each set of eight sclk cycles. in clock mode 01, the total conversion time does not include the time required to turn on the internal reference. dac/gpio timing figures 10?3 detail the timing diagrams for writing to the dac and gpios. figure 10 shows the timing speci- fications for clock modes 00, 01, and 10. figure 11 shows the timing specifications for clock mode 11. figure 12 details the timing specifications for the dac input select register and 2 bytes to follow. output data is updated on the rising edge of sclk in clock mode 11. figure 13 shows the gpio timing. figure 14 shows the timing details of a hardware ldac command dac- register update. for a software-command dac-register update, t s is valid from the rising edge of cs , which fol- lows the last data bit in the software command word. ldac functionality drive ldac low to transfer the content of the input reg- isters to the dac registers. drive ldac permanently low to make the dac register transparent. the dac output typically settles from zero to full scale within ? lsb after 2?. see figure 14.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 38 ______________________________________________________________________________________ sclk din dout 1234 t cspwh t css t doe t ds t dh t dot t cl t ch t csh t dod 32 16 8 d15 d14 d13 d12 d11 5 d15 d7 d14 d6 d13 d5 d12 d4 d0 d1 d0 d1 cs figure 11. dac/gpio serial-interface timing (clock mode 11) sclk din dout cs 1289 24 bit 7 (msb) bit 6 bit 0 (lsb) the command byte initializes the dac select register the next 16 bits select the dac and the data written to it bit 15 bit 14 10 bit 0 bit 1 figure 12. dac-select register byte and dac serial-interface word
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 39 gpio input/output cs t gsu t god figure 13. gpio timing ldac t ldacpwl t s out_ 1 lsb figure 14. ldac functionality layout, grounding, and bypassing for best performance, use pc boards. ensure that digital and analog signal lines are separated from each other. do not run analog and digital signals parallel to one another (especially clock signals) or do not run digital lines underneath the max1221/MAX1223/max1343 package. high-frequency noise in the av dd power sup- ply may affect performance. bypass the av dd supply with a 0.1? capacitor to agnd, close to the av dd pin. bypass the dv dd supply with a 0.1? capacitor to dgnd, close to the dv dd pin. minimize capacitor lead lengths for best supply-noise rejection. if the power sup- ply is very noisy, connect a 10 resistor in series with the supply to improve power-supply filtering. the max1221/MAX1223/max1343 thin qfn packages contain an exposed pad on the underside of the device. connect this exposed pad to agnd. refer to the max1258evkit for an example of proper layout. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max1221/MAX1223/max1343 is measured using the end-point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. unipolar adc offset error for an ideal converter, the first transition occurs at 0.5 lsb, above zero. offset error is the amount of deviation between the measured first transition point and the ideal first transition point.
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 40 ______________________________________________________________________________________ bipolar adc offset error while in bipolar mode, the adc? ideal midscale transi- tion occurs at agnd -0.5 lsb. bipolar offset error is the measured deviation from this ideal value. adc gain error gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed and with a full-scale analog input voltage applied to the adc, resulting in all ones at dout. dac offset error dac offset error is determined by loading a code of all zeros into the dac and measuring the analog output voltage. dac gain error dac gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed, when loading a code of all ones into the dac. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital sam- ples, signal-to-noise ratio (snr) is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist fre- quency excluding the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all other adc output signals: sinad(db) = 20 x log (signal rms /noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the enob as follows: enob = (sinad - 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 6 are the amplitudes of the first five harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest distortion component. adc channel-to-channel crosstalk bias the on channel to midscale. apply a full-scale sine wave test tone to all off channels. perform an fft on the on channel. adc channel-to-channel crosstalk is expressed in db as the amplitude of the fft spur at the frequency associated with the off channel test tone. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. the intermodulation prod- ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2 f1). the individual input tone levels are at -7dbfs. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc so the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conver- sion result has decreased by -3db. note that the t/h performance is usually the limiting factor for the small- signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. thd x vvvvvv = ++++ () ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 1 log /
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 41 dac digital feedthrough dac digital feedthrough is the amount of noise that appears on the dac output when the dac digital con- trol lines are toggled. adc power-supply rejection adc power-supply rejection (psr) is defined as the shift in offset error when the power supply is moved from the minimum operating voltage to the maximum operating voltage. dac power-supply rejection dac psr is the amount of change in the converter? value at full-scale as the power-supply voltage changes from its nominal value. psr assumes the converter? lin- earity is unaffected by changes in the power-supply voltage. chip information transistor count: 58,141 process: bicmos
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports 42 ______________________________________________________________________________________ pin configurations ain0 ref1 gpioc0 n.c. ldac out7 res_sel cs gpioc1 eoc dv dd dgnd sclk din out0 gpioa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 agnd n.c. out4 out6 av dd out3 out2 out1 ref2/ain6 ain5 n.c. n.c. ain4 ain3 ain2 ain1 cnvst/ain7 thin qfn max1221 top view dout out5 gpioa1 ain2 ref1 n.c. ain0 ldac out7 res_sel cs ain1 eoc dv dd dgnd sclk din out0 cnvst/ain11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 agnd n.c. out4 out6 av dd out3 out2 out1 ain9 ain8 ain7 n.c. ain6 ain5 ain4 ain3 ref2/ain10 thin qfn MAX1223 dout out5 n.c. gpioa0 1 gpioa1 2 3 dv dd 4 dgnd 5 dout 6 sclk 7 din 8 out0 9 eoc ain0 27 ref1 26 25 gpioc0 24 n.c. 23 res_sel 22 21 20 d.c. 19 gpioc1 out1 10 out2 11 12 av dd 13 agnd 14 n.c. 15 d.c. 16 d.c. 17 d.c. 18 out3 36 ref2/ain6 35 34 n.c. 33 n.c. 32 ain4 31 ain3 30 ain2 29 ain1 28 ain5 ldac cs cnvst/ain7 max1343 top view thin qfn (6mm x 6mm x 0.8mm)
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports ______________________________________________________________________________________ 43 qfn thin.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1221/MAX1223/max1343 12-bit, multichannel adcs/dacs with fifo, temperature sensing, and gpio ports maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 1 12/07 changed timing characteristic specification 7

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